ADP1741ACPZ-R7

ADP1741 is a low dropout (LDO) CMOS linear regulator that operate from 1.6V to 3.6V and provide up to 2A of output current. This low VIN/VOUT LDO is ideal for regulation of nanometer FPGA geometries operating from 2.5V down to 1.8V I/O rails, and for powering core voltages down to 0.75V. Using an advanced, proprietary architecture, this provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7µF ceramic output capacitor. This allows an external soft start capacitor to be connected to program the start-up. A digital power-good output allows power system monitors to check the health of the output voltage. Typical applications are server computers, memory components, telecommunications equipment, network equipment, DSP/FPGA/microprocessor supplies, instrumentation equipment/data acquisition systems.

• Stable with small 4.7µF ceramic output capacitor, power-good indicator
• Excellent load and line transient response, logic-controlled enable
• Current-limit and thermal overload protection, reverse current protection
• Input voltage range from 1.6 to 3.6V (TJ=−40°C to +125°C, VIN=(VOUT + 0.4V) or 1.6V, IOUT=100mA)
• Shutdown current is 6µA max (EN=GND, VIN=3.6V, VIN=VOUT + 0.4V or 1.6V, IOUT=100mA, CIN=COUT=4.7µF)
• 0.75 to 3.3V adjustable output voltage range
• Dropout voltage is 10mV typ (IOUT=100mA, VOUT ≥ 1.8V, VIN=(VOUT + 0.4V) or 1.6V, TA=25°C)
• Output noise is 23µV rms typ (10Hz to 100KHz, VOUT=0.75V, VIN=(VOUT + 0.4V) or 1.6V, TA=25°C)
• 16-lead LFCSP-WQ package
• Temperature rating range from -40°C to +125°C

Opmerkingen

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