ADP1754ACPZ-1.8-R7

ADP1754ACPZ-1.8-R7 is a low dropout (LDO) CMOS linear regulator that operates from 1.6V to 3.6V and provides up to 1.2A of output current. This low VIN/VOUT LDO is ideal for regulation of nanometre FPGA geometries operating from 2.5V down to 1.8V I/O rails and for powering core voltages down to 0.75V. Using an advanced proprietary architecture, the ADP1754 provides a high power supply rejection ratio (PSRR) and low noise and achieves excellent line and load transient response with only a small 4.7µF ceramic output capacitor. The ADP1754 allows an external soft start capacitor to be connected to program the startup. A digital power-good output allows power system monitors to check the health of the output voltage. It is used in applications such as server computers, memory components, telecommunications equipment, network equipment, DSP/FPGA/microprocessor supplies, instrumentation equipment/data acquisition systems.

• 1.8V output voltage, input voltage range from 1.6V to 3.6V
• Stable with small 4.7µF ceramic output capacitor, excellent load and line transient response
• Current-limit and thermal overload protection, power-good indicator
• Logic-controlled enable, reverse current protection
• Operating supply current is 90µA typical at (IOUT = 500μA, TA = 25°C)
• Shutdown current is 2µA typical at (EN = GND, VIN = 1.6V, TA = 25°C)
• Fixed output voltage accuracy is +1% maximum at (IOUT = 10mA, TA = 25°C)
• Power supply rejection ratio is 65dB typical at (VIN = VOUT + 1V, IOUT = 10mA, 1KHz, VOUT = 0.75V)
• Output noise is 23µV rms typical at (10Hz to 100KHz, VOUT = 0.75V, TA = 25°C)
• Operating temperature range from -40°C to +125°C, 16-lead LFCSP-WQ package

Opmerkingen

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