Product Information
Product Overview
LTC6954 is a low phase noise, triple output clock, distribution divider/driver. This device has a three LVPECL outputs. Each output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output. It is widely used in application such as clocking high speed, high resolution ADCs, DACs and data acquisition systems, low jitter clock distribution etc.
- Low noise clock distribution: suitable for high speed/high resolution ADC clocking
- 1.8GHz maximum input frequency (when delay = 0)
- EZSync™ clock synchronization compatible
- Input slew rate is 100V/µs minimum
- Input duty cycle is 50% typical
- Three independent, low noise outputs
- Self bias voltage is 2.05V typical
- Supply current is 300mA typical
- Operating junction temperature is -40°C to 105°C
- Package style is 36-lead plastic QFN
Notes
ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party
Technical Specifications
Clock Distribution, Divider
3Outputs
3.45V
36Pins
105°C
-
No SVHC (27-Jun-2024)
1.8GHz
3.15V
QFN-EP
-40°C
-
MSL 1 - Unlimited
Technical Docs (2)
Legislation and Environmental
Country in which last significant manufacturing process was carried outCountry of Origin:Philippines
Country in which last significant manufacturing process was carried out
RoHS
RoHS
Product Compliance Certificate