S25FL512SDPMFVG10

S25FL512SDPMFVG10 is a FL-S flash non-volatile memory using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance, 65-nm process lithography. This family of devices connect to a host system via a SPI. This multiple width interface is called SPI multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256bytes) or 256 words (512bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 512Mb density, 65nm MirrorBit process technology, 66MHz DDR speed
• 16-pin SO package type
• Industrial plus temperature range from -40 to +105°C, EHPLC, SO footprint with RESET#
• Uniform 256kB sectors
• SPI clock polarity and phase modes 0 and 3
• Commands, Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
• Common flash interface (CFI) data for configuration information, programming (1.5MBps)
• Quad-input page programming (QPP) for slow clock systems, erase (0.5 to 0.65MBps)
• Cycling endurance, 100000 program-erase cycles, minimum
• Data retention, 20 year data retention, minimum, OTP array of 1024bytes