IS43TR16128DL-107MBL

IS43TR16128DL-107MBL is a 1866MT/s 128Mx16 2Gb DDR3 SDRAM. The memory controller initiates levelling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write levelling mode, the DQ pins are in undefined driving mode. During write levelling mode, only NOP or DESELECT commands are allowed, as well as an MRS command to exit write levelling mode. Since the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal. The controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from the controller. tWLMRD(max) timing is controller dependent.

• Standard voltage is VDD and VDDQ=1.5V ± 0.075V, low voltage (L): VDD and VDDQ=1.35V + 0.1V, -0.067V
• High-speed data transfer rates with system frequency up to 1066MHz
• 8 internal banks for concurrent operation, 8n-bit pre-fetch architecture
• Programmable CAS latency, programmable additive latency: 0, CL-1, CL-2
• Programmable CAS WRITE latency (CWL) based on tCK, programmable burst length: 4 and 8
• Programmable burst sequence: sequential or interleave, BL switch on the fly
• Auto self-refresh (ASR), self-refresh temperature (SRT), partial array self-refresh
• Asynchronous RESET pin, OCD (off-chip driver impedance adjustment)
• 96-ball BGA package
• Commercial temperature rating range from 0°C ≤ TC ≤ 95°C