HEF4020BT,652

The HEF4020BT is a 14-stage Binary Counter with a clock input (CP\), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 and Q3 to Q13). The counter advances on the high to low transition of CP\. A high on MR clears all counter stages and forces all outputs low, independent of the state of CP\. Each counter stage is a static toggle flip-flop. A feature of the device is its high speed (typical 35MHz at VDD = 15V). It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.

• High speed operation
• Fully static operation
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B

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